@inproceedings{vijayaraghavan-etal-2026-symdirec,
    title = "{SYMDIREC}: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced {RTL} Synthesis and Summarization",
    author = "Vijayaraghavan, Prashanth  and
      Nitsure, Apoorva  and
      Shi, Luyao  and
      Mackin, Charles  and
      Jadhav, Ashutosh  and
      Beymer, David  and
      Degan, Ehsan  and
      Mukherjee, Vandana",
    editor = {Matusevych, Yevgen  and
      Eryi{\u{g}}it, G{\"u}l{\c{s}}en  and
      Aletras, Nikolaos},
    booktitle = "Proceedings of the 19th Conference of the {E}uropean Chapter of the {A}ssociation for {C}omputational {L}inguistics (Volume 5: Industry Track)",
    month = mar,
    year = "2026",
    address = "Rabat, Morocco",
    publisher = "Association for Computational Linguistics",
    url = "https://preview.aclanthology.org/ingest-eacl/2026.eacl-industry.66/",
    pages = "886--899",
    ISBN = "979-8-89176-384-5",
    abstract = "Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves {\textasciitilde}20{\%} higher Pass@1 rates for synthesis and 15{--}20{\%} ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks."
}