Automated Program Repair (APR) is vital for software maintenance. Despite notable advancements, existing methods still face challenges of insufficient bug dependency modeling and inadequate global repair planning when addressing semantically complex multi-location bugs. We propose CascadeFix, a multi-location automatic repair method via cascading planning and generation. Firstly, to improve the modeling of semantic and structural dependencies among bugs, three types of bug relationships-Use, Copy, and Nearby-are defined to characterize semantic connection, patch reusability, and contextual interference. Then, to address inadequate global repair planning, a cascading repair planning algorithm is designed to effectively cluster strongly correlated bugs and intelligently assign reasonable repair priorities and operations to each cluster, ensuring the rationality and consistency of global repair. Finally, taking clusters as the basic repair units, a cascading patch generation mechanism is proposed to dynamically integrate intra-cluster dependency information and cross-cluster repair knowledge, producing patches that maintain syntactic correctness and semantic consistency under global dependency constraints. Experiments on Defects4J show that CascadeFix resolves 84 multi-location bugs, achieving a 31% improvement over current state-of-the-art methods.

LLMs often fail in hardware vulnerability detection due to the intrinsic semantic concurrency of HDLs (Hardware Description Language), where vulnerabilities arise from the interaction of multiple concurrent execution statements rather than a single sequential execution path. To address the problem, we propose VerilogLAVD, a LLM-Aided Vulnerability Detection framework by generating executable Traversal Detection Patterns (TDPs), i.e. the rules describing how to find the evidence of vulnerabilities in Verilog HDL. We first introduce a Unified Verilog Property Graph (VeriPG) that explicitly models parallel semantics by combining AST, CFG, and DDG. Furthermore, a semantic validation mechanism is designed to constrain and filter the LLM-generated TDPs. By executing these validated TDPs on VeriPG, our method produces stable and deterministic detection results. Experiments demonstrate that VerilogLAVD improves the F1 score by 133% compared to LLM-based methods. Furthermore, the framework successfully identifies real-world hardware vulnerabilities in open-source hardware design repositories.

Large Language Models (LLMs) have achieved remarkable success in natural language processing (NLP), particularly in single-turn question answering (QA) on short-text. However, their performance significantly declines when applied to multi-turn QA over extra-long context (ELC), as they struggle to capture the logical correlations across multiple chunks of ELC and maintain the coherence of multi-turn Questions. To address the challenges, we propose the CSTree-SRI framework (Cognitive Semantic Tree through Summarization, Retrieval, and Introspection). CSTree-SRI dynamically constructs the CSTree to preserve logical coherence within ELC through hierarchical synthesis and introspective validation. Then a logic-driven traversal strategy on CSTree is designed to provide efficient information retrieval for question answering. Additionally, we construct a suite of multi-turn QA datasets and an evaluation benchmark tailored for ELC tasks, and comprehensive experiments demonstrate the framework’s superiority in addressing the challenges of multi-turn QA over ELC.